Physical Design Training is a 4 month course(+1 month for fresher’s covering Device basics, Digital Design concept, network analysis,DSM IC Fabrication Flow) structured to enable aspiring engineers to get in-depth knowledge of all aspects of Physical design flow from Netlist to GDSII including Floor planning, power planning, Placement, Clock Tree Synthesis(CTS) and Routing.
The course enables you to acquire knowledge, skills and practical experience across the entire Backend ASIC Flow (Netlist to GDSII).
The Course includes In-Class Sessions, Lab exercises and Industry Standard Projects that our students are put through instills confidence and the analytical abilities required to work on complex industry’s challenges in various Deep Sub - Micron Technology Process Nodes.
Knowledge on below topics is required.
1.Knowledge of digital Electronics fundamentals.
2.Knowledge of CMOS fundamentals.
3.Knowledge of Verilog / VHDL is a plus
4.Knowledge of ASIC / SOC design flow is a plus.
VLSI Design Flow
Fundamentals of Semiconductor Devices.
Overview of transistor theory and network analysis
Introduction to Linux Commands and Tcl scripting.
Physical Design Flow (Netlist to GDSII).
Libraries and Inputs files information: LEF, LIB, SDC, Netlist, DEF, SPEF, UPF and CPF
Sanity checks for Libraries, netlist, timing etc
Die Area selection
Power mesh creation
Defining Power Structures
Logical PG Connections
PG Pin Connections
Create Power rails etc
Standard cell placement techniques
congestion analysis timing analysis
Clock tree creation
spec files creation
clock tree analysis
Signal routing, congestion analysis
Static IR analysis
Dynamic IR analysis
*Practical labs and projects ranging from beginner to advance level which cover latest trends in industry
Working Professionals from VLSI industry, currently working in some area (RTL Design, Verification, FPGA Design, analog layout, Synthesis, STA, characterization, board level testing..etc.) , but want to switch to Physical design (PD).
Engineers planning to make career in VLSI backend flow.
Verification engineers planning to gain complete flow exposure.
Engineering college faculty looking to enhance their VLSI skill set.
The trainer is working as Lead Physical Design Engineer with a leading VLSI Company in Bangalore and has 10+ years of Physical Design experience in VLSI industry, with multiple complex tape outs to his credit.
He is passionate about teaching and mentored many entry / mid-level engineers throughout his corporate career. He is excellent Trainer and rich experience of working on complex SOC backend flow in various technologies from 45nm to 7nm.