Custom layout training is 3 to 4 months training course targeted for fresher’s, B.Tech, BE, MTech, ME graduates planning to make careers as a layout design engineer in various aspects of layout including analog layout, memory layout, standard cell layout and I/O layout. Custom layout design course ensures that a fresher engineer is prepared including ASIC Row, VLSI Design flow, Digital Design concepts, CMOS basics, FinFET basics, Standard cell, IO’s and detailed analog layout techniques. Course also includes training on UNIX, revision management, scripting and soft skill for effective interview performance.
Conductor, Semiconductor & Insulators
Basic Passive and Active devices, R, C, L, RC RL and RLC Circuits
Ohms law, Kirchhoff laws, KVL and KCL and all theorems
Basic of circuit understanding.
MOSFET Basics, Operations, CMOS circuits & second order effects.
CMOS Detailed fabrication process.
FinFET working, Fabrication, advantages & disadvantages.
Std Cell Layout
IO Layout Guidelines
Sense amplifier & Bit cell development
Why memory layout different than analog layout
Fixing few manually created leaf-cell errors which impact Abutment issues
Impact of IR, EM and DFM
Pitch Calculation for blocks
What is Analog Layout
Difference between Analog and RF Layout
concepts Matching, Current mirror
Analog Circuits & Layout guidelines
Single & Multi stage differential opamp layout
current mirror layout
Latch Up and antenna concepts
LDO and other regulators
ADCs & DACs
input pair, differential routing, Power routing, offset minimizing
Power/Signal IR Drop
Cross-talk and coupling
Deep Submicron Layout Issues
Shallow Trench Isolation (LOD)
Well Proximity Effect
The trainer is working as Lead Physical Design Engineer with a leading VLSI Company in Bangalore and has 10+ years of Physical Design experience in VLSI industry, with multiple complex tape outs to his credit.
He is passionate about teaching and mentored many entry / mid-level engineers throughout his corporate career. He is excellent Trainer and rich experience of working on complex SOC backend flow in various technologies from 45nm to 7nm.